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Jan 20-23, 2026

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SILICON PROVEN

Physical AI needs a new last-meter link

We engineered an electric-field PHY that enables always-on, low-latency edge AI across your personal devices.

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Engineering the Second Nervous System for Physical AI Co-pilots

  • Human-AI collaboration demands continuous context.
  • Continuous context lives in your personal space.
  • The last-meter link is the bottleneck.
  • RF radiates. Confinement wins.
  • So we built Electro-Quasistatic (EQS) connectivity in silicon.

1 mW at 5 Mbps • < 1 ms latency • Private by physics

Gen 3

SILICON SHIPPING

From 0.01Mbit/s prototype to 5 Mbit/s production silicon in just 4 years (2021 to 2025)

Team

Built by Silicon Veterans

We are an ultra-low-power mixed-signal team that turns first-principles physics into shipped silicon. We have lived through tapeouts, bring-up, characterization, and adoption

  • AI-accelerated design: 5-month tapeout cycles
  • 25+ patents filed annually on novel physics
  • Full-custom low-power optimization for every block
Shreyas Sen, CTO of Ixana

Shreyas Sen

CTO

Inventor of Wi-R; Elmore Associate Prof. at Purdue; Co-pioneer of USB-C

Angik Sarkar, CEO of Ixana

Angik Sarkar

CEO

Serial founder with prior exit; Ex-Intel; PhD Purdue ECE

Shovan Maity, Head of Research of Ixana

Shovan Maity

Head of Research

Architect of first Wi-R chip; Led 10+ tapeouts; PhD Purdue

Bob Twomey, EVP Sales of Ixana

Bob Twomey

EVP Sales

Ex-Decawave CRO; Led global UWB adoption; Ex-Qualcomm VP

Execution Velocity

From fundamental physics to production silicon

2025

Commercial Launch & Dev Kits

Production-grade silicon shipping to partners

2024

World's First Wi-R Video Stream

Gen 2 Silicon achieves high-bandwidth milestone

2023

First Wi-R Silicon Sampling

Gen 1 Chip debut at CES '23

2021

Proof of Concept Silicon

0.01Mbit/s prototype proves the physics

2016-2020

The Physics Era

Foundational Research at Purdue University

Validated Silicon

Shipping to Partners

Our XA-NFE2001 transceiver is validated, characterized, and shipping to major device manufacturers. Secure your evaluation kit and start designing the future.

CES 2024 Innovation Award
CES INNOVATION AWARDHONOREE 2024
EE Times Silicon 100 banner
EE TIMES SILICON 100RECOGNIZED
NATO Innovation Challenge
NATO INNOVATION CHALLENGE3rd PLACE WINNER
40+ PATENTSE-FIELD & MIXED-SIGNAL

The Partner Ecosystem

The Silicon Choice for Always-On Intelligence

From Tier-1 OEMs to advanced defense research, leading organizations rely on our silicon to break the power barrier. We provide the foundational connectivity for the upcoming always-on AI co-pilot decade.

Research Partners

Purdue University

Purdue University

National Science Foundation

NSF

Government & Defense

U.S. Army

U.S. Army

SOCOM

USSOCOM

Defense Innovation Unit

Defense Innovation Unit

U.S. Air Force

U.S. Air Force

Industry Partners

Tier-1 Smartphone OEM

Tier-1 Smartphone OEM

Tier-1 Wearables Partner

Tier-1 Wearables Partner

Tier-1 Platform Partner

Tier-1 Platform Partner

Culture & Careers

Architect the Second Nervous System

We are building the silicon backbone of the AI era. This requires more than standard design, it demands first-principles thinking. Join the team that is closing the gap between biological and digital intelligence, from equation to tapeout.

From Physics to Product

We design novel mixed-signal architectures from first principles. We treat physics as the only hard constraint, ignoring industry convention.

Architect the New Standard

Build the foundational connectivity layer that the next generation of physical AI will rely on.

High-Velocity Execution

We move fast. With 5-month tapeout cycles and rapid validation, you will see your designs in silicon faster than anywhere else in the industry.